1. Field of the Invention
The present invention relates generally to semiconductor memory cells and more particularly to nonvolatile random access memory cells fabricated of silicon carbide.
2. Description of the Prior Art
Memory comes in three basic forms (1) dynamic storage in which data must be constantly refreshed and in which data are erased when power is no longer applied to the cell; (2) non-volatile memory in which data remains permanently in the cell even when power is not applied; and (3) static memory which does not need to be refreshed but which loses its data when power is no longer applied to the cell. The type of memory chosen depends on the performance requirements of the memory cell. Density is important to the system due to Cost, size, and performance considerations. The delay along signal lines comprises much of the delay in modern high speed computers. Smaller, denser components allow for the use of shorter signal lines and therefore improve performance. Also, the smaller the memory cell, the less expensive the integrated memory chip and the less expensive the overall memory system.
Dynamic random access memory cells (DRAM) are well known in the industry and are typically constructed of a single transistor and a single storage capacitor. Metal oxide semiconductor field effect transistor dynamic random access memory (MOSFET DRAM) is currently the dominant main memory technology. MOSFET DRAMs are chosen primarily for their characteristics of low cost, low power, and moderate performance; DRAMs achieve their low cost through use of a relatively simple semiconductor technology (CMOS) and a small memory cell consisting of the single transistor and the single storage capacitor. The CMOS technology provides both n-channel and p-channel field effect transistors. The equivalent circuit of a typical DRAM circuit cell is shown in FIG. 1.
The DRAM stores information as a charge in the storage capacitor which is coupled through the source drain path of the transistor to a bit line. The gate path of the transistor is then coupled to a word line. When the word and bit lines are simultaneously addressed (brought to a high voltage), the access transistor is turned on and charge is transferred into the storage capacitor if it had no charge initially (stored "zero"), or little charge is transferred to the storage capacitor if it were fully charged initially (stored "one"). The amount of charge that the bit line must supply to the storage capacitor is measured by the sensing circuitry, and this information is used to, interpret whether a "zero" or "one" had been stored in the cell. The sense circuity then restores full charge in the capacitor if it had been there originally, or fully depletes the capacitor if little charge had existed originally.
Thus, the charge in the storage capacitor must be refreshed repetitively due to destructive readout of the memory charge as well as from leakage currents both from the capacitor and from the transistor. Edge effects are one way in which leakage currents occur. Edge effects are when one is not able to shut off the transistor properly and therefore there is still some residual current conduction through the transistor along the edges of the transistor. Typically, the memory contents are refreshed about every 2 ms. The refresh operation is accomplished through special control circuits built into the memory cell array. The refresh operation prohibits full usage of the memory because a given amount of time is required to periodically refresh all the memory cells. In the event of a power failure, the memory Contents cannot be refreshed and therefore the information in the memory is lost.
At present, a true non-volatile random access memory with long term retention, unlimited cycling and fast read/write capabilities are not readily available. Thus, in many applications, battery backed SRAM or a DRAM is employed. If the application does not demand many read/write cycles, an EPROM or an EEPROM may be used. EPROMS and EEPROMS have very slow write speed and limited cycling capability. Battery backed SRAMs or DRAMs require bulky battery packs. Magnetic Storage is not only bulky but also has inherent reliability problems as any mechanical system with rotating parts. In addition, none of the aforementioned memory types can operate above 200.degree. C.
Silicon carbide is a wide energy bandgap semiconductor (approximately 3 eV), and is thus an attractive material for the fabrication of integrated circuitry. Silicon carbide offers high saturated electron velocity (approximately 2.0.times.10.sup.7 cm/s), and high breakdown electric field (approximately 2.times.10.sup.6 V/cm), and high thermal conductivity (approximately 5 W/cm -.degree.C.). In addition, the energy bandgap and thus the maximum operating temperature range of silicon carbide is at least twice that of conventional semiconductors.
Historically, n-channel MOSFETs fabricated of conventional semiconductor materials such as silicon have been made by ion implanting n-type source and drain regions in a p-type substrate. The industry has been unable to apply this technology to silicon carbide to produce desirable results. Significant technology impediments have prevented the incorporation of silicon carbide into such transistors. These impediments include (1) ion implantation has yet to be fully characterized in silicon carbide; (2) the dopant in p-type silicon carbide (usually aluminum) incorporates itself in the gate oxide causing poor oxide interfacial (silicon dioxide-silicon carbide) properties; and (3) electron mobilities in inversion layer of p-type silicon carbide are very low (10-20 cm.sup.2 /V).
MOSFETs constructed of silicon carbide are described in a paper entitled "Thin Film Deposition and Microelectronic and Optoelectronic Device Fabrication and Characterization in Monocrystaline Alpha and Delta Silicon Carbide" by Robert F. Davis et al., which appeared in Volume 79, No. 5 of the Proceedings of the IEEE (May 1991). Davis et al. disclose a typical inversion mode MOSFET constructed on a p-type 6H epi layer and having n+ source and drain contacts. This design suffers the drawback that a good quality oxide cannot be grown on the p-type silicon carbide epitaxial layer. The oxide cannot be grown effectively on the epitaxial layer because the p-type silicon carbide incorporates aluminum which interferes with the silicon carbide/oxide interface.
In International Application No. PCT/US92/10210 to Cooper et al., an NVRAM cell design fabricated of silicon carbide is shown describing two separate approaches. The first is a bipolar transistor with a p-n junction diode and the second is a MOS transistor with a MOS capacitator. In the bipolar transistor approach, the effective storage capacitance is made of two reverse biased junctions--one in the storage diode and the second in the reversed biased junction of the bipolar transistor. Both the junctions contribute to the leakage current of the cell. Thus, the total leakage current in the bipolar transistor approach is twice of what it would be in a single junction approach.
In the MOS transistor approach of Cooper et al., the enhancement mode n-channel MOS transistor is made as an inversion mode transistor on p-type silicon carbide substrate with n+ conductivity type source and drain regions. Such a transistor may tend to have a high leakage current and poor transconductance due to high interface state density at the silicon dioxide/p-silicon carbide interface due to the incorporation of aluminum which is used as a dopant in the p-type silicon carbide material. In fact, Cooper et al. discuss on page 19, line 19 that this design offers a sub-threshold leakage current at room temperature for this type of transistor of 1.95 .mu.A. This sub-threshold leakage current value is unacceptable for NVRAM applications. Furthermore, the MOS transistor approach of Cooper et al. utilizes a storage capacitor of MOS-type made on an n+ silicon carbide layer. Such a capacitor will tend to have a high leakage current due to the defects in the n+ silicon carbide layer and also the defects in the underlying p-type silicon carbide substrate.